The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A non-volatile semiconductor memory (NVSM) drive (e.g., a flash drive) includes NVSM and operates based on a size of a page of data. For example, data transferred to and from the NVSM is grouped into data sets. Each of the data sets has a length equal to the length of one or more pages of data. A page of data may have a length of, for example, 8 kilobytes (KB).
A NVSM drive may include, for example, an NVSM interface, a buffer managing module, an error correction code (ECC) module, an interface management module and a NVSM control module. The NVSM interface may communicate with a host. Data is transferred between the NVSM interface and the host. The buffer managing module receives data from the host prior to being stored in the NVSM and receives data from the NVSM prior to being transferred to the host. The ECC module encodes data provided to the NVSM and decodes data received from the NVSM. The interface management module controls data transfers between the ECC module and the NVSM.
The NVSM control module generates descriptors in response to access request signals received from the host. The descriptors may indicate, for example, whether a read operation or a program (i.e. write) operation is to be performed, the amount of data to be transferred, and the addresses to access in the NVSM. The ECC module and the interface management module are operated based on the descriptors.
The interface control module communicates with the NVSM via multiple channels (e.g., 8 channels per NVSM chip) and includes a first-in-first-out (FIFO) register for each of the channels. The FIFO registers are accessed sequentially during read and program operations. The size of each of the FIFO registers is equal to the size of one or more pages of data.
During a program operation, the ECC module transfers data in a page-based format to the interface control module prior to being stored in the NVSM. The ECC module may transfer one or more pages (M pages) of data to each of the FIFO registers, where M is an integer greater than or equal to 1. The number of pages the ECC module transfers to each of the FIFO registers is dependent on the page format of that NVSM drive. For each set of M pages transferred a single descriptor is generated.
For example, if the ECC module is operating in an NVSM drive with a single page format, 1 page of data is transferred to each of the FIFO registers. In this example, the size of each of the FIFO registers is equal to the size of 1 page of data. If the ECC module is operating in an NVSM drive with a dual page format, then 2 pages of data are transferred to each of the FIFO registers and the size of each of the FIFO registers is equal to the size of 2 pages of data. The M pages of data are transferred to a current FIFO register prior to transferring data to a next (or subsequent) FIFO register. The above-described data transfers are performed in reverse for a read operation.
Because data is not transferred to a next FIFO register until a current FIFO register receives the M pages of data, data transfer delays can result. These delays may be experienced at one or more of the FIFO registers and can increase with higher order page formats. The order of a page format refers to the number of pages transferred during a single data transfer event. A data transfer event refers to transferring data to or from one of the channels of the NVSM. For example, in a NVSM drive with a 2-page format, if a “bottleneck” arises at a first FIFO register due to speed differences between the ECC module and a first channel, delays can arise at the first FIFO register and at all subsequent FIFO registers. Since two pages of data are transferred to a single FIFO register, a second page of data can be delayed when a first page of data is delayed. Also, delays in transferring the second page of data to the first FIFO register delays transfers of data to FIFO registers subsequent to the first FIFO register.